仿真建模动态响应误差5%指标测试数据

基于模型与平台，以I/O或通信方式提供了9个及以上系统硬件在环实时仿真测试端口；开展了关键控制保护装置的功能与性能测试，包括基本功能测试、稳态性能测试、动态/暂态性能测试。结合CPU/FPGA混合仿真技术方案，实现关键电力电子装置实时仿真步≤2.5μs；验证了关键电力电子装置的控制保护系统仿真建模动态响应误差≤5%。

Based on dedicated simulation models and platforms, this dataset provides 9 or more hardware-in-the-loop (HIL) real-time simulation test ports for power systems via I/O or communication interfaces. Functional and performance tests have been conducted on key control and protection devices, including basic functional tests, steady-state performance tests, and dynamic/transient performance tests. By adopting the hybrid CPU/FPGA simulation technology solution, the real-time simulation step size for key power electronic devices is controlled to be ≤2.5 μs. The dynamic response error of the simulation modeling for the control and protection system of these key power electronic devices is verified to be ≤5%.