基于CMOS工艺的阻变存储器工艺平台测试数据集

本数据集为课题4考核指标4.1：RRAM嵌入40nm logic 工艺开发。课题4研究基于CMOS 工艺进行阻变存储器材料和工艺技术研究，基于40nm 及以下CMOS 大生产工艺建立阻变存储器及模拟计算芯片制造工艺平台，确定阻变存储器及模拟计算芯片的制造工艺流程和设备选型，实现基于阻变存储器的模拟计算芯片流片验证；研究模拟计算阵列和芯片制造的良率提升及高可靠量产技术，对影响阻变存储器阵列比特良率的关键工艺进行重点优化，推进模拟计算芯片技术的量产应用。
本数据集命名为2020YFB2206004-001-工艺平台，数据量约为2.25MB，共包含14个图片：图片内容重点为显示华力制造RRAM结构嵌入40nm Logic 后段结构，其中可以观察RRAM 结构，RRAM结构嵌入40nm后段Metal 4和Metal 5 之间的状态，MOSFET放大图，栅极结构状态和尺寸，完整的MOSFET及后段金属的全局图。

This dataset corresponds to Assessment Indicator 4.1 of Project 4: Development of 40nm Logic Process with Embedded RRAM.

Project 4 conducts research on RRAM materials and process technologies based on CMOS processes. Its objectives include establishing a manufacturing process platform for RRAM and analog computing chips using 40nm and below CMOS mass production processes, confirming the manufacturing flow and equipment selection for RRAM and analog computing chips, and achieving tape-out verification of analog computing chips based on RRAM. Additionally, the project researches yield improvement and high-reliability mass production technologies for analog computing arrays and chip manufacturing, focuses on optimizing key processes that affect the bit yield of RRAM arrays, and promotes the mass production and application of analog computing chip technologies.

This dataset is named 2020YFB2206004-001-Process Platform, with a total size of approximately 2.25 MB and contains 14 images in total. The images primarily showcase the back-end-of-line (BEOL) structure of 40nm Logic with embedded RRAM manufactured by Huali, including the RRAM structure itself, the state of the RRAM structure embedded between Metal 4 and Metal 5 in the 40nm BEOL, magnified views of MOSFETs, the status and dimensions of the gate structure, and overall views of complete MOSFETs and back-end metal layers.