Data and code underlying the research of: CCO-ADC for CIM Acclerators

This targets image classification applications. This work presents a memory-periphery co-design to perform accurate A/D conversions of analog matrix-vector-multiplication (MVM) outputs. A novel scheme is introduced where select-lines and bit-lines in the memory are virtu- ally fixed to improve conversion accuracy and aid a ring-oscillator-based A/D conversion, equipped with component sharing and inter-matching of the reference blocks. In addition, we deploy a self-timed technique to further ensure high robustness addressing global design and cycle-to-cycle variations. The concept is demonstrated using a 4Kb CIM chip prototype using resistive bitcells on TSMC 40nm CMOS technology. This dataset includes schematic netlist files, chip photos, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

本数据集面向图像分类应用场景。本研究提出一种存储-外设协同设计（memory-periphery co-design）方案，以实现对模拟矩阵向量乘法（Matrix-Vector-Multiplication, MVM）输出信号的高精度模数转换（Analog-to-Digital, A/D）。该方案创新性地将存储器内的选择线与位线进行虚拟固定，以提升转换精度，并辅助基于环形振荡器的模数转换流程，同时实现参考模块的组件共享与相互匹配。此外，本研究采用自定时技术，进一步保障了高鲁棒性，可应对全局设计偏差与周期间波动。该设计概念通过采用台积电（TSMC）40纳米互补金属氧化物半导体（Complementary Metal-Oxide Semiconductor, CMOS）工艺的阻变存储单元搭建的4千比特计算内存（Compute-in-Memory, CIM）芯片原型得到验证。本数据集包含以下内容：电路原理图网表文件、芯片实物照片、用于延迟与功耗估算/仿真结果的Excel格式原始数据，以及用于生成相关学术论文中图表的MATLAB代码。