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The architectures are written in Verilog HDL, simulated using IES-XL-15.2 tools, and synthesized using the Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. Here power, timing, and area reports have been generated.

本数据集涉及的硬件架构均采用Verilog硬件描述语言（Verilog HDL）编写，使用IES-XL-15.2工具完成仿真验证；随后采用Genus综合工具19.1版，在45纳米工艺节点下，基于楷登（Cadence）厂商提供的通用约束库完成逻辑综合。架构功耗的计算以64×64像素的图像为输入，并以20MHz的工作频率作为测试条件。本次研究已生成涵盖功耗、时序与面积的完整分析报告。