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In this article, we propose a highly sensitive vertically plug-in source drain contacts high Schottky barrier based bilateral gate and assistant gate controlled bidirectional tunnel field Effect transistor (VPISDC-HSB-BTFET). It can achieve much more sensitive forward current driving ability than the previously proposed High Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Silicon body of the proposed VPISDC-HSB-BTFET is etched into a U-shaped structure. By etching both sides of the silicon body to form vertically plug-in source drain contacts, the source and drain electrodes are plugged into a certain height of the vertical parts of both sides of the U-shaped silicon body. Thereafter, the efficient area of the band-to-band tunneling generation region near the source drain contacts is significantly increased, so as to achieve sensitive ON-state current driving ability. Comparing to the mainstream FinFET technology, lower subthreshold swing, lower static power consumption and Higher Ion−Ioff ratio can be achieved.

本文提出一款高灵敏度垂直插入式源漏接触高肖特基势垒双边栅极辅助栅极控制双向隧穿场效应晶体管（VPISDC-HSB-BTFET）。相较于此前报道的基于高肖特基势垒源漏接触的双边栅极辅助栅极控制双向隧穿场效应晶体管（HSB-BTFET），该器件具备更为优异的正向电流驱动灵敏度。所提出的VPISDC-HSB-BTFET的硅本体被蚀刻为U型结构，通过对硅本体两侧进行蚀刻以形成垂直插入式源漏接触，使源漏电极插入至U型硅本体两侧垂直部分的指定高度位置。此后，源漏接触区域附近的带间隧穿产生区有效面积得到显著提升，进而实现高灵敏度的导通态电流驱动能力。与主流鳍式场效应晶体管（FinFET）工艺相比，该器件可实现更低的亚阈值摆幅、更低的静态功耗以及更高的开态-关态电流比。