FPGA-Based Implementation of IEEE 754 Single Precision Floating Point Multiplier

This paper presents an efficient implementation of a single-precision floating point multiplier compliant with the IEEE 754 standard, optimized for deployment on a Xilinx Virtex-5 FPGA. The design is developed using VHDL and follows a pipelined architecture to ensure high performance while maintaining technology independence. It includes mechanisms for handling overflow and underflow conditions; however, rounding is intentionally omitted to preserve higher precision, particularly for applications such as Multiply and Accumulate (MAC) operations. The implemented multiplier achieves a performance of 301 MFLOPs with a latency of three clock cycles. Functional verification was carried out against the Xilinx floating point IP core to ensure correctness.