Flexible Network Modal Packet Processing Pipeline Construction Mechanism for Cloud-Network Convergence Environment

ObjectiveWith the deep integration of information network technologies and vertical application domains, the demand for cloud-network convergence infrastructure becomes increasingly significant, and the boundaries between cloud computing and network technologies are gradually fading. The advancement of cloud-network convergence technologies gives rise to diverse network service requirements, creating new challenges for the flexible processing of multimodal network packets. The device-level network modal packet processing flexible pipeline construction mechanism is essential for realizing an integrated environment that supports multiple network technologies. This mechanism establishes a flexible protocol packet processing pipeline architecture that customizes a sequence of operations such as packet parsing, packet editing, and packet forwarding according to different network modalities and service demands. By enabling dynamic configuration and adjustment of the processing flow, the proposed design enhances network adaptability and meets both functional and performance requirements across heterogeneous transmission scenarios.MethodsConstructing a device-level flexible pipeline faces two primary challenges: (1) it must flexibly process diverse network modal packet protocols across polymorphic network element devices. This requires coordination of heterogeneous resources to enable rapid identification, accurate parsing, and correct handling of packets in various formats; (2) the pipeline construction must remain flexible, offering a mechanism to dynamically generate and configure pipeline structures that can adjust not only the number of stages but also the specific functions of each stage. To address these challenges, this study proposes a polymorphic network element abstraction model that integrates heterogeneous resources. The model adopts a hyper-converged hardware architecture that combines high-performance switching ASIC chips with more programmable but less computationally powerful FPGA and CPU devices. The coordinated operation of hardware and software ensures unified and flexible support for custom network protocols. Building upon the abstraction model, a protocol packet flexible processing compilation mechanism is designed to construct a configurable pipeline architecture that meets diverse network service transmission requirements. This mechanism adopts a three-stage compilation structure consisting of front-end, mid-end, and back-end processes. In response to adaptation issues between heterogeneous resources and differentiated network modal demands, a flexible pipeline technology based on Intermediate Representation (IR) slicing is further proposed. This technology decomposes and reconstructs the integrated IR of multiple network modalities into several IR subsets according to specific optimization methods, preserving original functionality and semantics. By applying the IR slicing algorithm, the mechanism decomposes and maps the hybrid processing logic of multimodal networks onto heterogeneous hardware resources, including ASICs, FPGAs, and CPUs. This process enables flexible customization of network modal processing pipelines and supports adaptive pipeline construction for different transmission scenarios.Results and DiscussionsTo demonstrate the construction effectiveness of the proposed flexible pipeline, a prototype verification system for polymorphic network elements is developed. As shown in Fig. 6, the system is equipped with Centec CTC8180 switch chips, multiple domestic FPGA chips, and domestic multi-core CPU chips. On this polymorphic network element prototype platform, protocol processing pipelines for IPv4, GEO, and MF network modalities are constructed, compiled, and deployed. As illustrated in Fig. 7, packet capture tests verify that different network modalities operate through distinct packet processing pipelines. To further validate the core mechanism of network modal flexible pipeline construction, the IR code size before and after slicing is compared across the three network modalities and allocation strategies described in Section 6.2. The integrated P4 code for the three modalities, after front-end compilation, produces an unsliced intermediate code containing 32,717 lines. During middle-end compilation, slicing is performed according to the modal allocation scheme, generating IR subsets for ASIC, CPU, and FPGA with code sizes of 23,164, 23,282, and 22,772 lines, respectively. The performance of multimodal protocol packet processing is then assessed, focusing on the effects of different traffic allocation strategies on network protocol processing performance. As shown in Fig. 9, the average packet processing delay in Scheme 1 is significantly higher than in the other schemes, reaching 4.237 milliseconds. In contrast, the average forwarding delays in Schemes 2, 3, and 4 decrease to 54.16 microseconds, 32.63 microseconds, and 15.48 microseconds, respectively. These results demonstrate that adjusting the traffic allocation strategy, particularly the distribution of CPU resources for GEO and MF modalities, effectively mitigates processing bottlenecks and markedly improves the efficiency of multimodal network communication.ConclusionsExperimental evaluations verify the superiority of the proposed flexible pipeline in construction effectiveness and functional capability. The results indicate that the method effectively addresses complex network environments and diverse service demands, demonstrating stable and high performance. Future work focuses on further optimizing the architecture and expanding its applicability to provide more robust and flexible technical support for protocol packet processing in hyper-converged cloud-network environments.

研究背景与目标：随着信息网络技术与垂直应用领域的深度融合，云网融合基础设施的需求日益凸显，云计算与网络技术的边界也逐渐模糊。云网融合技术的演进催生了多样化的网络服务需求，为多模态网络报文的灵活处理带来了新的挑战。设备级网络模态报文处理灵活流水线构建机制是实现多网络技术兼容的集成化环境的核心支撑，该机制构建了灵活的协议报文处理流水线架构，可根据不同的网络模态与业务需求，自定义报文解析、报文编辑、报文转发等一系列操作流程。通过实现处理流程的动态配置与调整，所提设计提升了网络适配能力，可满足异构传输场景下的功能与性能双重需求。

研究方法：构建设备级灵活流水线面临两大核心挑战：其一，需在多态网元设备中灵活处理多样化的网络模态报文协议，这要求协调异构资源，实现对各类格式报文的快速识别、精准解析与正确处理；其二，流水线构建需保持灵活性，提供可动态生成与配置流水线结构的机制，该机制不仅可调整流水线的阶段数量，还可修改每个阶段的具体功能。为应对上述挑战，本研究提出了一种集成异构资源的多态网元抽象模型。该模型采用超融合硬件架构，将高性能交换专用集成电路（Application-Specific Integrated Circuit，ASIC）芯片与可编程性更强但计算能力相对较弱的现场可编程门阵列（Field-Programmable Gate Array，FPGA）以及中央处理器（Central Processing Unit，CPU）设备相结合。软硬件协同运行可实现对自定义网络协议的统一灵活支持。基于该抽象模型，本研究设计了协议报文灵活处理编译机制，用于构建可适配多样化网络业务传输需求的可配置流水线架构。该机制采用前端、中端、后端三级编译架构。针对异构资源与差异化网络模态需求之间的适配问题，本研究进一步提出了基于中间表示（Intermediate Representation，IR）切片的灵活流水线技术。该技术可根据特定优化方法，将多网络模态的集成中间表示分解并重构为若干中间表示子集，同时保留原始功能与语义。通过应用IR切片算法，该机制可将多模态网络的混合处理逻辑分解并映射至ASIC、FPGA、CPU等异构硬件资源。该过程可实现网络模态处理流水线的灵活自定义，并支持针对不同传输场景的自适应流水线构建。

结果与讨论：为验证所提灵活流水线的构建有效性，本研究开发了一套多态网元原型验证系统。如图6所示，该系统搭载了Centec CTC8180交换芯片、多款国产FPGA芯片以及国产多核CPU芯片。在该多态网元原型平台上，本研究构建、编译并部署了针对互联网协议第4版（IPv4）、GEO、MF三种网络模态的协议处理流水线。如图7所示，报文捕获测试验证了不同网络模态通过各自独立的报文处理流水线运行。为进一步验证网络模态灵活流水线构建的核心机制，本研究针对第6.2节中提及的三种网络模态与分配策略，对比了切片前后的IR代码体量。三种模态的集成P4代码经前端编译后，会生成未切片的中间代码，共计32717行。在中端编译阶段，本研究根据模态分配方案执行切片操作，分别生成适用于ASIC、CPU与FPGA的中间表示子集，其代码体量分别为23164行、23282行与22772行。随后，本研究对多模态协议报文处理性能进行了评估，重点分析了不同流量分配策略对网络协议处理性能的影响。如图9所示，方案1的平均报文处理时延显著高于其余方案，达到4.237毫秒。相比之下，方案2、3、4的平均转发时延分别降至54.16微秒、32.63微秒与15.48微秒。上述结果表明，调整流量分配策略——尤其是针对GEO与MF模态的CPU资源分配——可有效缓解处理瓶颈，显著提升多模态网络通信效率。

结论：实验验证表明，所提灵活流水线在构建有效性与功能性能方面均具备优势。实验结果显示，该方法可有效应对复杂网络环境与多样化业务需求，展现出稳定且优异的性能。未来研究将进一步优化该架构并拓展其应用范围，为超融合云网环境下的协议报文处理提供更可靠、更灵活的技术支撑。