36-Bit Minicomputer Using SRAM ICs as Logic Elements

This is a design-in-progress for a 36-bit, 20 MIPS, open-source minicomputer that uses synchronous static RAM ICs as logic elements, plus a minimal amount of glue logic. This dataset contains netlists, firmware, a virtual machine for simulating the ALU, a discrete event simulator for simulating the entire computer with wire delays, an assembler, a circuit board layout, and software written in C and Python for producing all of the foregoing. A Ph.D. dissertation that describes and documents this work is included as a separate file. Significant portions of this work in simulation correctly, but the entire machine is not yet something that can be built in operable form.

本数据集为一款处于研发阶段的36位、20百万条指令每秒（Million Instructions Per Second，MIPS）开源小型计算机的设计方案，该机型采用同步静态RAM集成电路（synchronous static RAM ICs）作为逻辑元件，并搭配少量胶合逻辑电路。本数据集包含网表（netlist）、固件、用于仿真算术逻辑单元（Arithmetic Logic Unit, ALU）的虚拟机、支持线延迟仿真的全机离散事件模拟器、汇编器、电路板布局文件，以及用于生成上述所有内容的C语言与Python语言编写的配套软件。另有一份详细阐述并记录该研发项目的博士学位论文作为独立文件包含在内。该项目的多数模块在仿真环境中可正常运行，但整套计算机暂无法以可工作的实体形态完成搭建。