DFS_DESYNCH

The DFS_DESYNCH dataset contains power traces of a software AES implementation running on a 32-bit RISC-V System-on-Chip (SoC). The SoC incorporates a Dynamic Frequency Scaling (DFS) unit that randomly adjusts the operating frequency between 35MHz and 60MHz.Curated by: hardware-fabLicense: Open Data Commons License cc-by-4.0 The dataset is designed to aid research in side-channel analysis methodologies.DFS_DESYNCH was created to support the DLaTA methodology for resynchronizing power traces collected under frequency scaling. The code for DLaTA is publicly available on GitHub.

DFS_DESYNCH数据集包含运行于32位RISC-V片上系统（System-on-Chip，SoC）的软件实现的高级加密标准（Advanced Encryption Standard，AES）算法的功耗轨迹。该片上系统集成了动态频率缩放（Dynamic Frequency Scaling，DFS）单元，可在35MHz至60MHz的区间内随机调整工作频率。本数据集由hardware-fab整理，采用开放数据通用许可协议（Open Data Commons License cc-by-4.0）进行授权。本数据集旨在助力边信道分析（side-channel analysis）方法学领域的研究。DFS_DESYNCH的构建初衷是支持针对频率缩放场景下采集的功耗轨迹进行重同步的DLaTA方法，DLaTA的相关代码已在GitHub平台公开获取。