Implementation and verification of real- time nuclear signal pile-up and separation algorithm based on FPGA

[Background] In the field of nuclear detection, real-time processing of detector signal at high count-rate is necessary. In high count-rate environments, the problem of nuclear signal pile-up can affect the analysis of subsequent results, so it is necessary to process the pile-up signal. The commonly used solution currently is to use pile-up recognition to reject, but this method can cause loss of counts and has limitations in some applications such as timing analysis. [Purpose] This study proposes a real-time pile-up separation algorithm that performs fast/slow shaping processing on the original signal. [Methods] Fast shaping used the triangular shaping method to obtain the arrival time of the nuclear signal to determine whether pile-up occurred; Slow shaping adopted the trapezoidal shaping method to extract the energy information of the nuclear signal. At the same time, by using the symmetrical rising/falling edge features of the trapezoidal signals, the pile-up signal was separated according to the time point of pile-up occurrence to improve the counting performance of the system. The algorithm was simple and computationally efficient, making it easy to implement in field programmable gate array (FPGA). [Results] In the simulation test experiment, the proposed algorithm effectively increased the count rate by 4% to 26.5% while ensuring the accuracy of separation. In the radioactive source experiment, within the tested count rate range, the proposed algorithm effectively increased the count rate by 6.8% to 13.5%. [Conclusion]The results of this study provide a new separation method for pile-up signal processing in high count-rate environments.

[背景] 在核探测领域中，对探测器信号开展高计数率下的实时处理是必要需求。在高计数率环境中，核信号脉冲堆积问题会对后续结果分析造成干扰，因此需对堆积信号进行处理。当前主流的解决方案为采用堆积识别剔除法，但该方法会造成计数损失，且在时序分析等部分应用场景中存在局限性。[目的] 本研究提出一种针对原始信号开展快慢成形处理的实时脉冲堆积分离算法。[方法] 快速成形采用三角成形法获取核信号的到达时间，以此判断是否发生脉冲堆积；慢速成形则采用梯形成形法提取核信号的能量信息。同时，借助梯形信号对称的上升、下降沿特征，根据脉冲堆积发生的时间点实现堆积信号分离，以提升系统的计数性能。该算法结构简洁、计算效率高，易于在现场可编程门阵列（FPGA）中实现。[结果] 在仿真测试实验中，所提算法在保证分离精度的前提下，可将计数率提升4%至26.5%；在放射源实验中，于测试的计数率范围内，该算法可使计数率提升6.8%至13.5%。[结论] 本研究结果为高计数率环境下的堆积信号处理提供了一种全新的分离方案。