SSD-SMR Write Cache Strategy for Optimizing Long-Tail Latency Based on Q-Learning

With the continuous increase in the scale of global data, the effective and inexpensive improvement of data access performance is an important challenge faced by storage systems. An effective solution is to build cache systems using low-latency, high-bandwidth Solid-State Drives (SSD) and low-cost, high-storage-density Shingled Magnetic Recording (SMR). However, the inherent mechanical motion and multitrack stacking characteristics of SMR result in poor write performance, and the frequent write-back of dirty data in SSD to SMR may cause severe long-tail latency owing to the large number of Read-Merge-Write (RMW) operations. To this end, a cache replacement optimization strategy combining a reinforcement learning Q-Learning algorithm is proposed based on the SSD-SMR hybrid storage architecture. By learning the empirical relationship between the I/O load status and the latency of the SMR devices, write operations to the SMR can be controlled. When the SMR load is high, controlling the eviction of dirty data in the cache can reduce the number of RMW operations caused by SMR write-backs, thereby optimizing the tail latency overhead of the system under different loads. The Q-Learning algorithm is combined with the data-popularity-based caching algorithm LRU and the SMR aware caching algorithm SAC and tested using real enterprise Trace and simulated Trace generated by YCSB. The experimental results show that the proposed method can effectively improve the performance of existing caching algorithms, reducing the average latency by 57.06% and tail latency by 87.49%.