基于CMOS工艺的阻变存储器晶圆良率测试数据集

本数据集为课题4考核指标4.2：阻变存储器晶圆良率。课题4研究基于CMOS 工艺进行阻变存储器材料和工艺技术研究，基于40nm 及以下CMOS 大生产工艺建立阻变存储器及模拟计算芯片制造工艺平台，确定阻变存储器及模拟计算芯片的制造工艺流程和设备选型，实现基于阻变存储器的模拟计算芯片流片验证；研究模拟计算阵列和芯片制造的良率提升及高可靠量产技术，对影响阻变存储器阵列比特良率的关键工艺进行重点优化，推进模拟计算芯片技术的量产应用。
本数据集命名为2020YFB2206004-002-晶圆良率，数据量约为7.26MB，共包含13个图片和3份excel原始数据：数据重点呈现在完成RRAM嵌入40nm Logic 后段后，测试其关键电学性能及结构良率，主要包括稳定的高低阻转变性能和晶圆内不同位置的性能一致性，表征电学性能达标，结构良率达标。

This dataset corresponds to Assessment Indicator 4.2 of Project 4: Wafer Yield of Resistive Random-Access Memory (RRAM). Project 4 conducts research on RRAM materials and process technologies based on CMOS manufacturing processes. It aims to build a manufacturing process platform for RRAM and analog computing chips using 40nm and below CMOS mass production processes, confirm the manufacturing flow and equipment selection for RRAM and analog computing chips, and complete the tape-out verification of analog computing chips based on RRAM. Additionally, it researches yield improvement and high-reliability mass production technologies for analog computing arrays and chip manufacturing, focuses on optimizing key processes that affect the bit yield of RRAM arrays, and promotes the mass production and practical application of analog computing chip technologies. This dataset is named 2020YFB2206004-002-Wafer Yield, with a total size of approximately 7.26 MB, containing 13 images and 3 original Excel data files. The core data focuses on testing the key electrical properties and structural yield after integrating RRAM into the back-end of 40nm Logic process. The tested contents mainly include stable high-low resistance switching performance and performance consistency across different positions on the wafer, which verifies that both the electrical performance and structural yield meet the required standards.

搜集汇总

背景与挑战

背景概述

该数据集聚焦于基于40nm及以下CMOS工艺的阻变存储器（RRAM）晶圆良率测试，包含图片和Excel原始数据，重点评估RRAM嵌入逻辑后段后的关键电学性能（如高低阻转变）和结构良率，以验证性能达标和提升量产技术，属于国家重点研发计划项目的一部分。