Accelerating scientific computations with mixed precision algorithms

Abstract
On modern architectures, the performance of 32-bit operations is often at least twice as fast as the performance of 64-bit operations. By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many dense and sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution. The approach presented here can apply not only to conventional processors but also to other technologies such as Field Programmab...

Title of program: ITER-REF
Catalogue Id: AECO_v1_0

Nature of problem
On modern architectures, the performance of 32-bit operations is often at least twice as fast as the performance of 64-bit operations. By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many dense and sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution.

Versions of this program held in the CPC repository in Mendeley Data
AECO_v1_0; ITER-REF; 10.1016/j.cpc.2008.11.005

This program has been imported from the CPC Program Library held at Queen's University Belfast (1969-2019)

摘要
在现代计算架构中，32位运算的性能通常至少为64位运算的两倍。通过结合使用32位与64位浮点运算，众多稠密与稀疏线性代数算法的性能可得到显著提升，同时仍能保证最终求解结果的64位精度。本文提出的方法不仅可应用于传统处理器，还可适用于其他技术，例如现场可编程（Field Programmab...）

程序名称：ITER-REF
目录编号：AECO_v1_0

问题本质
在现代计算架构中，32位运算的性能通常至少为64位运算的两倍。通过结合32位与64位浮点运算，众多稠密与稀疏线性代数算法的性能可获得显著提升，同时维持求解结果的64位精度。

该程序在Mendeley数据的CPC程序库中的版本信息如下：
AECO_v1_0；ITER-REF；10.1016/j.cpc.2008.11.005

本程序源自贝尔法斯特女王大学托管的CPC程序库（1969-2019年）