Dataset for Modelling Gate-Oxide-Short Defects in FinFET 3D Structure and Development of Associated Fault Models for Complex Logic Gates

FinFET manufacturing process for 16 nm technology was simulated using the Sentaurus TCAD ‘sprocess’ tool provided by Synopsys. The process was simulated for both the defect-free triangular FinFET as well as the defective FinFET with Gate-Oxide-Short by introducing pinholes in different locations of the gate. FinFET electrical characteristic curves were acquired through simulations with the Sentaurus TCAD ‘sdevice’ tool. Based on the BSIM-CMG local extraction process and the characteristic curves obtained from TCAD, the HSPICE model parameters for NFinFET and PFinFET transistors were extracted. Matlab scripts were used to calculate an initial estimate for the parameters related to the subthreshold slope, threshold voltage, drain-induced-barrier-lowering, and effective-oxide-thickness. The difference currents and capacitances for all pinhole scenarios were modelled as Verilog-A modules to be applied in circuit-level simulations. Circuit-level simulations were performed with the aid of extracted HSPICE model parameters for triangular-fin FinFET and the developed defect models for various pinhole scenarios.

本研究采用新思科技（Synopsys）提供的Sentaurus TCAD工艺仿真工具‘sprocess’，对16纳米制程的鳍式场效应晶体管（FinFET）制造工艺进行仿真。本次仿真覆盖两类场景：无缺陷的三角鳍型鳍式场效应晶体管，以及通过在栅极不同位置引入针孔以产生栅氧短路（Gate-Oxide-Short）的缺陷型鳍式场效应晶体管。通过Sentaurus TCAD器件仿真工具‘sdevice’开展仿真，获取鳍式场效应晶体管的电学特性曲线。基于BSIM-CMG局部参数提取流程与TCAD仿真所得的特性曲线，提取N型鳍式场效应晶体管（NFinFET）与P型鳍式场效应晶体管（PFinFET）的HSPICE模型参数。利用Matlab脚本计算与亚阈值斜率、阈值电压、漏致势垒降低（drain-induced-barrier-lowering）及有效氧化层厚度相关参数的初始估算值。将所有针孔场景下的差分电流与电容建模为Verilog-A模块，以供电路级仿真使用。基于三角鳍型鳍式场效应晶体管的提取得到的HSPICE模型参数，以及针对各类针孔场景开发的缺陷模型，开展电路级仿真。