Logical Fault Detection Approach for Mixed Control Flipping Faults in Reversible Circuits

Due to the rapid development of computing machines in terms of micro-architectural designs, millions of transistors are involved per chip, which leads to complex digital circuit design and meets the demands of more computational power. It indicates that a single transistor’s size is advancing at the atomic scale in future computing technologies. The gain of loss-less bit information in reversible logic computation is highly acceptable in modern computing devices. Therefore, motivated by these, researchers have explored the reversible logic concept for applying newer technologies such as quantum computing, optical computing, nanotechnology, DNA computing, digital communication systems, low-power CMOS design, etc. In the current literature, numerous developments on synthesis and optimization in reversible circuits have been proposed. Simultaneously, in order to observe the correct behavior of reversible circuits in terms of performing the correct functionality and integrity performance, testing plays an important role. In this article, we consider a fault model labeled the Mixed Control Flipping Fault (MixCFF) model that is applied in the reversible circuit, which is also relevant to the quantum circuits for representing the faults. The proposed work presents an automatic test pattern generation (ATPG) algorithm to detect the MixCFF. The proposed MixCFF model enables the correlation between the existing fault models in the reversible circuit, which are also presented in the proposed work. Experimental results are evaluated based on the MixCFF detection and the MixCFF fault coverage range with the help of different benchmark circuits using the suggested ATPG algorithm.