scale-lab/MetRex

--- license: bsd-3-clause --- # MetRex <!-- Provide a quick summary of the dataset. --> This dataset card contains Verilog modules along with their post-synthesis metrics (area, delay, static power) explained in natural language format. The synthesis results are obtained using [Yosys](https://github.com/YosysHQ/yosys) and the [Skywater](https://github.com/google/skywater-pdk) 130nm PDK. ## Dataset Details ## Use ``` # pip install datasets from datasets import load_dataset ds = load_dataset("scale-lab/MetRex", split="train") print(next(iter(ds))) ``` ## Data Splits The dataset only contains the training split. ## Citation ``` @INPROCEEDINGS{abdelatty2025metrex, author={M. {Abdelatty} and J. {Ma} and S. {Reda}}, booktitle={2025 30th Asia and South Pacific Design Automation Conference (ASP-DAC)}, title={MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs}, year={2025}, volume={}, number={}, } ```