Design and Implementation of a 32-Bit Five-Stage Pipelined RISC-V Processor (RV321)

This project documents the complete RTL design and verification of a 32-bit, five-stage pipelined processor implementing the RISC-V RV32I instruction set. The processor is developed in synthesizable Verilog HDL with a modular architecture featuring the core pipeline stages, control logic, ALU operations, immediate generation, memory interfaces, and pipeline registers. Hazard detection, data forwarding, and branch-handling mechanisms ensure correct operation under data and control dependencies. Functional and timing verification were performed using Intel Quartus II, confirming accurate instruction execution, stable pipeline operation, and proper management of stalls and forwarding scenarios. The uploaded material provides a clear, structured representation of the processor’s architecture, implementation flow, simulation results, and verification methodology. It serves as a useful reference for learning pipelined CPU design, RTL development, and RISC-V architecture fundamentals.