database.rar
收藏DataCite Commons2025-06-01 更新2024-07-29 收录
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https://figshare.com/articles/dataset/database_rar/21060442/1
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资源简介：
The architectures are written in Verilog HDL, simulated using IES-XL-15.2 tools, and synthesized using the Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. Here power, timing, and area reports have been generated.
提供机构：
figshare
创建时间：
2022-09-08
