A Sub-THz CMOS Molecular Clock with 20 ppt Stability at 10,000 s Based on A Dual-Loop Spectroscopic Detection and Digital Frequency Error Integration
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http://dataverse.jpl.nasa.gov/citation?persistentId=doi:10.48577/jpl.PNE4BB
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资源简介：
This paper presents a dual-loop chip-scale molecular clock (CSMC), which enhances the Allan Deviation performance by combining high signal-to-noise ratio of using fundamental mode and long-term stability of using higher order modes in derivative molecular absorption spectroscopy. In addition, digital frequency-error integration is adopted in the frequency-locked loop to provide an infinite open-loop DC gain, which fully suppresses any frequency drift caused by the temperature-sensitive crystal oscillator. This new generation CSMC is implemented in 65-nm CMOS, and achieves 20 ppt (part-per-trillion) Allan Deviation at 10,000 s averaging time with 71-mW power consumption
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Root
创建时间：
2023-02-04
