Chip-level Trojan Benchmark from Trust-Hub

The submited dateset consist of 32 different trojan-inserted IP cores design. For each IP core design, the dataset provides some files that contain source code written in VHDL or Verilog design language. Some of the functions inside those files are malicious and some of them are clean. The malicious functions usually appear inside a conditional statement that rarely executed. That's why we extract machine learning feature from those conditional statements.

本次提交的数据集包含32种植入木马的IP核（IP core）设计方案。针对每一款IP核设计方案，该数据集提供了若干采用VHDL或Verilog硬件描述语言编写的源代码文件。这些文件中的部分功能模块为恶意代码，其余则为正常无害的功能。恶意功能模块通常隐藏于极少执行的条件语句内，正因如此，我们从这些条件语句中提取机器学习（machine learning）特征。

搜集汇总

背景与挑战

背景概述

该数据集包含32个特洛伊木马插入的IP核心设计，提供VHDL/Verilog源代码文件，其中恶意功能隐藏在条件语句中。数据集还包含从条件语句提取的机器学习特征，用于硬件木马早期检测模型的改进。