Data supporting the research on Advancing Spin-Qubit Architectures - Challenges, Design Guidelines, and Optimization Frameworks

This work investigates scalable semiconductor single-spin qubit architectures from a full-stack, hardware–software co-design perspective. We develop and evaluate a native compilation + design-space exploration framework (SpinQ) that maps realistic quantum circuits onto spin-qubit hardware models under operational constraints (e.g., limited connectivity, shared control, shuttling-based routing), and we quantify outcomes using metrics such as gate/depth overhead and an Estimated Success Probability (ESP) that incorporates operational errors, crosstalk, and decoherence. Methodology: implement architecture-aware compilation passes (including scalable routing via shuttling/SWAP abstractions), run systematic simulation-based benchmarking across many circuit workloads, and perform large-scale design-space exploration to identify trade-offs and design guidelines.