MESO standard cell models

The proposed SystemVerilog MESO models offer significantly faster simulation capabilities compared to the physical model [1], improving simulation speed while preserving essential accuracy. This enhancement enables the design of more complex circuits, including MESO cells, standard cells, and intellectual property (IP) blocks, while incorporating time multiplexing techniques.The development of this MESO-based standard cell library follows a systematic process: first, the basic MESO cell is simulated using a physical SPICE and Verilog-A model to measure key parameters, such as transition time. Next, a behavioral MESO cell model is created in SystemVerilog based on these parameters. Following this, a behavioral MESO-based majority gate is designed. Finally, behavioral MESO-based standard cells, including OR, NOR, AND, and NAND gates, are constructed using the MESO-based majority gate.