Data for Simulating and Optimizing Tapped Delay Lines for Time-to-digital Converters in FPGA using a Precision Model based on Circuit Characteristics
收藏Figshare2025-08-07 更新2026-04-28 收录
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https://figshare.com/articles/dataset/Data_for_b_Simulating_and_Optimizing_Tapped_Delay_Lines_b_b_for_Time-to-digital_Converters_in_FPGA_using_a_b_b_Precision_Model_based_on_Circuit_Characteristics_b_/29237618
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资源简介：
This is the data used to produce results for Simulating and Optimizing Tapped Delay Lines for Time-to-digital Converters in FPGA using a Precision Model based on Circuit Characteristics. It contains TDL delay and skew obtained from Vivado.
创建时间：
2025-08-07
