Supporting data for "Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices"

Third-generation nanopore sequencers offer a feature called selective sequencing or Read Until that allows genomic reads to be analyzed in real-time and abandoned halfway if not belonging to a genomic region of interest. This selective sequencing opens the door to important applications such as rapid and low-cost genetic tests. The latency in analyzing should be as low as possible for selective sequencing to be effective so that unnecessary reads can be rejected as early as possible. However, existing methods that employ a subsequence Dynamic Time Warping (sDTW) algorithm for this problem are too computationally intensive that a massive workstation with dozens of CPU cores still struggles to keep up with the data rate of a mobile phone-sized MinION sequencer. In this paper, we present Hardware Accelerated Read Until (HARU), a resource-efficient hardware-software co-design-based method that exploits a low-cost and portable heterogeneous Multiprocessor System-on-Chip (MPSoC) platform with on-chip Field-Programmable Gate Arrays (FPGA) to accelerate the sDTW-based Read Until algorithm. Experimental results show that HARU on a Xilinx FPGA embedded with a 4-core ARM processor is around 2.5×faster than a highly optimized multi-threaded software version (around 85×faster than the existing unoptimized multi-threaded software) running on a sophisticated server with 36-core Intel Xeon processor for a SARS-CoV-2 dataset. The energy consumption of HARU is two orders of magnitudes lower than the same application executing on the 36-core server. The open-source code for HARU sDTW module is available at https://github.com/beebdev/HARU and an example application that utilizes HARU is available at https://github.com/beebdev/sigfish-haru.