Characterization of a Low-Cost FPGA-based Time-to-Digital Converter with Maximized Readout Speed

This dataset includes: (i) code density test results obtained from 116272 collected samples; (ii) Differential and integral nonlinearities (DNL and INL) of uncalibrated and calibrated outputs calculated from estimated widths of delay elements; and (iii) Graphs of measured bin widths, bin width distribution, comparison of ideal, uncalibrated, and calibrated transfer functions, uncalibrated DNL and INL, and calibrated DNL and INL.