energy_efficient

the SPEC2017 checkpoint is generated by nemu(https://github.com/OpenXiangShan/NEMU(opens in new window)) with riscv-pk, then simulating with xs-gem5(https://github.com/OpenXiangShan/GEM5(opens in new window)).contentcsv: resultMakefile: place it to nemu root directory, run make checkpointing to generate checkpointgen_spec.py: place it to/riscv-rootfs/rootfsimg/ directory. Using it to generate rootfs*.cc, *.hh, BranchPredictor.py: src files in gem5procedurecheckpoint generation```git clone https://github.com/OpenXiangShan/NEMUgit submodule update --initexport NEMU_HOME=/path/to/NEMUmake checkpoint```gem5all src files are located in `src/cpu/pred/ftb`, BranchPredictor.py is placed in src/cpu/pred,it contains configuration of Branch Predictor. Most of the logic resides in ftb.cc and decoupled_bpred.cc.Some options in BranchPredictor.py can be used to control the activation of certain components：- enabletbit- enableNST- enableNBTafter generate checkpoints, usebuild/RISCV/gem5.fast --outdir=${OUTPUT_DIR}_run configs/example/fs.py --caches --l2cache --xiangshan-system --cpu-type=DerivO3CPU --mem-type=DRAMsim3 --dramsim3-ini=/home/lizilin/projects/xs_gem5/xiangshan_DDR4_8Gb_x8_2400.ini --mem-size=8GB --cacheline_size=64 --l1i_size=32kB --l1i_assoc=8 --l1d_size=32kB --l1d_assoc=8 --l2_size=1MB --l2_assoc=8 --l2-hwp-type=MultiPrefetcher --l3cache --l3_size=8MB --l3_assoc=8 --bp-type=DecoupledBPUWithFTB --cpu-clock='3.5GHz' --sys-clock='3.5GHz' --warmup-insts=20000000 --maxinsts=40000000 --generic-rv-cpt=checkpoints/${BENCH}/take_cpt/${BENCH}_${POS}_${WEIGHT}/0/_${POS}_.gz --gcpt-restorer=NEMU/resource/gcpt_restore/build/gcpt.binto run gem5. statistics are available in stats.txt. Some relevant statistics are:system.cpu.branchPred.predTimessystem.cpu.branchPred.condSaveTimesystem.cpu.branchPred.indirectSaveTimesystem.cpu.branchPred.noBranchStreamsystem.cpu.branchPred.indirectStreamsystem.cpu.branchPred.directStreamsystem.cpu.branchPred.condStreamsystem.cpu.branchPred.allStream