A 56 GS/s 8 Bit Time‐Interleaved ADC in 28 nm CMOS

This paper presents a real‐time output 56 GS/s 8 bit time‐interleaved analog‐to‐digitalconverter (ADC), where the full‐speed converted data are output by 16‐lane transmitters. A 64‐way8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancyis utilized to achieve a high linearity and high‐power efficiency. A low‐power ring voltage‐con‐trolled oscillator‐based injection‐locked phase‐locked loop combining with a phase interpolator‐based time‐skew adjuster is developed to generate the 8 equally spaced sampling phases. Digitalgain correction, digital‐detection‐analog‐correction offset calibration, and coarse–fine two‐steptime‐skew calibration are combined to optimize the ADC’s performances. An edge detector andphase selector associated with a common near‐end data‐transmission position and far‐end data‐collection instant are designed to avoid reset competition and implement deterministic latency. Fab‐ricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset‐gain calibrationand time‐skew calibration, respectively. The ADC core occupies an area of 1.2 mm 2 and consumes432 mW power consumption.