"A 1.2 kV Cell-Pitch-Efficient JBS-Integrated SiC MOSFET with Charge-Balanced P+ Layer for Enhanced Blocking Capability"

"A novel cell-pitch-efficient JBS-integrated SiC MOSFET with a charge-balanced P+ layer (CBP-JMOS) is proposed, addressing the inherent limitations of specific on-resistance (Ron,sp) increase and blocking capability degradation in existing JBS-integrated designs. A JBS diode integration approach without enlarging the cell-pitch is proposed to avoid on-resistance increase, while a charge-balanced P+ layer (CBP) is introduced to enhance the breakdown voltage (BV). The CBP-JMOS is systematically characterized through 3D TCAD simulations. Compared with conventional planar MOSFET, the CBP-JMOS achieves a 0.47\u00d7 reduction in third-quadrant voltage drop, faster switching speed with a 0.89\u00d7 reduction in switching loss, and a 124 V increase in BV. Notably, these enhancements are achieved with only a marginal increase in Ron,sp. Overall, the CBP-JMOS provides an improved trade-off among conduction, blocking, and switching performance."