Reproducibility Artifact: From Factor Reuse to Sparse Setup in Transient SPICE

Reproducibility artifact for the manuscript “From Factor Reuse to Sparse Setup: A Stage-Resolved Review and Workload-Aware Characterization of Transient SPICE.” The artifact supports a stage-resolved, workload-aware performance characterization of transient SPICE. It contains the exact C++ research-kernel source snapshot, build and benchmark scripts, MOS–RC netlist generators, generated benchmark decks, frozen bottleneck-prediction protocol, raw stage profiles, processed results, waveform-validation data, literature-search records, screening decisions, DOI audit, and SHA-256 checksums. The benchmark evidence includes six public IBM power-grid transients, controlled nonlinear MOS–RC scaling up to 500,000 nodes, full-period pulse and sinusoidal experiments, and a public-derived C7552 topology containing 41,588 nodes and 97,373 devices. The nonlinear performance campaign contains 42 successful formal runs, with three independent profiled repetitions per configuration, plus six pilot runs. The frozen mechanism rule correctly identifies the dominant measured stage in 11 of 12 workloads. The unsuccessful prediction for the 500,000-node MOS–RC case and an exploratory C7552 long-interval convergence failure are retained and disclosed rather than removed or used to retune the rule. The C7552 workload preserves the public gate hierarchy and extracted R/C topology, but replaces unsupported SkyWater BSIM4 wrappers with level-1 MOS devices. Its formal 20 ps interval is therefore an assembly/setup characterization of a realistic public-derived topology, not a claim of SkyWater PDK fidelity or complete functional logic validation. IBM benchmark inputs and official reference traces are not redistributed because they remain under the control of the original distributor. The artifact records their official source location, checksums, derived profiles, and processed validation results. No cross-simulator performance ranking is claimed.