Data and code underlying the research of: SRIF-ADC for CIM accelerators

This targets neuromorphic and general-purpose arithmetic applications. A <em>scalable and reliable integrate and fire circuit </em>ADC (SRIF-ADC) design for CIM architectures is presented, suitable for stringent power and area constraints. Techniques to stabilize the node receiving analog in-puts are implemented that allow more rows to be activated at the same time, thereby improving the scalability in terms of higher parallelism of operations. A self-timed variation-aware design approach is introduced along with design measures to drastically reduce the read disturb of memristor devices. In addition, a compact, built-in sample-and-hold circuit to replace the typically used large-sized capacitance is present along with a built-in weighting technique to alleviate the need for post-processing when combining outputs of different bit significance. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

本数据集面向神经形态（neuromorphic）与通用算术类应用场景。针对计算内存（Compute-in-Memory, CIM）架构，本文提出了一种可扩展可靠型积分点火电路模数转换器（SRIF-ADC）设计方案，可满足严苛的功耗与面积约束要求。通过采用稳定模拟输入接收节点的技术，可实现同时激活更多阵列行，进而凭借更高的运算并行度提升系统可扩展性。本方案同时引入了自定时变异性感知设计方法，搭配可大幅降低忆阻器（memristor）器件读干扰的优化设计手段。此外，本设计采用紧凑型内置采样保持电路替代了传统使用的大尺寸电容，并搭配内置加权技术，可在合并不同比特权重的输出结果时省去后期后处理步骤。本数据集包含原理图网表文件、用于延迟与功耗评估及仿真结果的Excel原始数据表，以及用于生成相关论文中图表的Matlab代码。