RISC-V based Testing of the XOR-Free Polar Encoder and Decoder

Polar codes have revolutionized the error correction field by setting new benchmarks for efficient data transmission with high reliability. Polar codes are designed to achieve the maximum possible channel capacity, making them ideal for a modern communication system like 5G/6G. This paper presents two configurations for integrating the polar encoder and decoder in Vivado Intellectual Property (IP) Integrator. In the first configuration, the register transfer level (RTL) code of the polar encoder and decoder are directly wrapped to Vivado native IPs and utilized for real-time data transmission via universal asynchronous receiver transmitter (UART). The RTL code is encapsulated in the second configuration into a custom Advanced eXtensible Interface (AXI) IP to enable communication with processing systems (PS) such as MicroBlaze or ZYNQ. The first approach is demonstrated on the Zed board Zynq-7000 FPGA core. In contrast, the second configuration is implemented on an Arty A-7 35T FPGA board featuring RISC-V-based processors, such as Vega microprocessors. A hardware-software (HW-SW) co-simulation environment is also proposed in this paper to validate the functionality of the proposed polar encoder and decoder.