Consistent and Repeatable Transistor Level TID Transistor Array Measurement

TOTAL ionizing dose (TID) induced threshold voltage (Vt) shifts limit reliability in integrated circuits (ICs) used in spacecraft. Deposited electron hole pairs are subject to recombination. However, less mobile holes can be trapped as fixed positive charge, altering the (front gate) Vt [1-3]. Core (logic) transistors in a modern silicon on insulator (SOI) process have thin enough front gates so that little or no charge is collected, so charge TID primarily affects the buried oxide (BOX) [3-4]. Both NMOS and PMOS devices experience TID induced Vt shifts in the same direction from trapped positive charges, so TID decreases PMOS transistor current drive and leakage and increases NMOS current drive and leakage. Therefore, to characterize and thus model the reliability of ICs intended for spaceflight, the transistor level TID response must be characterized. This summary describes a transistor array designed to support that characterization, fabricated on a fully depleted SOI (FDSOI) 22 nm process [5]. The current vs. voltage (I-V) fidelity of measured transistors is very good. Higher multiplexer voltages allow choice of bias to remove unwanted multiplexer artifacts. The extracted Vt shift vs. dose trajectories show excellent consistency between identical and similar devices.