Electrical testing of high-resistance silicon substrate MOS arrays
收藏DataCite Commons2026-03-18 更新2026-05-05 收录
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A MOS array was fabricated on a 130nm 3k Ω· cm high resistance silicon substrate, and the leakage current characteristics, output curves, and transfer curves of NMOS and PMOS were tested under high substrate negative bias, respectively, as a preliminary study for MAPS chips.
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Science Data Bank
创建时间：
2026-03-18
