Research Data for "FPGA Design and Evaluation of an Access-Restricted Arbiter-PUF Interface With Root-Keyed SM4 Mapping"

This dataset supports the manuscript "FPGA Design and Evaluation of an Access-Restricted Arbiter-PUF Interface With Root-Keyed SM4 Mapping." It contains the research data and reproducibility material used to evaluate the implemented access-restricted Arbiter-PUF interface, including the 1.25-million-record physical modeling dataset, predefined data-split manifests, public-only modeling results, service-semantics and latency traces, routed FPGA implementation results, measurements from two Artix-7 boards, and thermal and recovery measurements. The files are organized by experiment and are accompanied by a README, file inventory, and SHA-256 checksums. Security-sensitive internal materials that are not required to reproduce the reported public-interface results are not included.