Evaluation of a fault-tolerant RISC-V

The RISC-V architecture is an initiative of academia and industry for embedded systems solutions. This architecture consists of a set of instructions developed to be open and free, facilitating and optimizing the implementations. Although its specification is open, the solutions currently available do not meet the requirements of some applications, such as space applications. Thus, our research team developed a RISC-V soft-core processor focusing on the implementation of fault tolerance techniques for use in embedded computer systems in critical environments. We intend to use the ChipIr facility to produce a realistic evaluation of the reliability of the developed RISC-V processor in an actual radioactive environment. The outcome of this study will allow us to evince the behavior of the processor core in a real critical environment.