A Synthetic 8-Station SMT Assembly-Line Dataset for Benchmarking SPC Detection of Stealthy Cyber-Physical Attacks

This is a fully synthetic, calibrated dataset and open-source simulator for an 8-station surface-mount technology (SMT) electronics-assembly line, built to benchmark statistical process control (SPC) and machine-learning detectors against stealthy, Stackelberg-game cyber-physical attacks. The release covers four independently-validated phases: Phase 1 (phase1_natural_variation.parquet) — 20,000 boards × 29 monitored process/inspection variables under natural, non-adversarial variation, generated by a Gaussian-copula dynamic factor model with six latent common-cause factors and calibrated marginal distributions. Phase 2 (phase2_attack_grid.parquet) — the same line under a grid of 4 attack families × 3 attacker-knowledge levels, layered on the Phase 1 baseline. Phase 3 (phase3_baseline_consequences.parquet, phase3_attack_consequences.parquet) — pass/rework/scrap classification, field-failure risk, and expected cost, labeling Phase 1's and Phase 2's output respectively. Phase 4 (phase4_detector_results.parquet) — results from an eight-method SPC/ML detector benchmark (Shewhart, CUSUM, EWMA, Hotelling T², MEWMA, isolation forest, PCA-T², autoencoder) evaluated against the Phase 2 attack grid and cross-referenced with Phase 3's cost labels. Every data file ships with a *.metadata.json sidecar recording its random seed, config hash, and exact library/OS versions. The accompanying smt-benchmark-v1.0.0-code.zip contains the full simulator, the YAML configs used to produce every file in this release, the test suite, and the calibration/validation reports — the entire dataset is regenerable byte-for-byte via: git clone (or unzip) → uv sync → uv run smt-benchmark generate --config configs/default_line.yaml Full modeling detail is documented in ATTACK_MODEL.md, CONSEQUENCE_MODEL.md, DETECTOR_BENCHMARK.md, and CALIBRATION.md inside the code archive. Licensed under the MIT License.