Koios benchmarks' netlist files (BLIF format)

Koios is a benchmark suite for FPGA architecture and CAD exploration. It contains circuits from the Deep Learning domain.

Here we are uploading the netlist files for these designs obtained by synthesizing the Verilog designs using Intel Quartus for Intel Stratix IV architecture. 

For more details see: 

https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/#koios-benchmarks

https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/verilog/koios