IBEX, AES, and JPEG circuits

该数据集包含了三个电路设计实例（IBEX、AES和JPEG），这些实例在两个技术节点（SKY130HD和ASAP7）下进行了评估。实验内容涉及对与电路设计和性能指标相关的参数进行优化，例如有效的时钟周期和布线长度。该数据集的规模覆盖了多个电路和技术节点，其任务旨在进行芯片设计优化。

This dataset comprises three circuit design cases: IBEX, AES, and JPEG, which were evaluated across two technology nodes: SKY130HD and ASAP7. The experiments involve optimizing parameters associated with circuit design and performance metrics, such as effective clock cycle and routing length. Spanning multiple circuits and technology nodes, this dataset is targeted at chip design optimization tasks.