<b>The Application of the Optimized Genetic Algorithm in SerDes Circuit Design</b>

This paper aims to solve the complex design problem of replacing inefficient, traditional parallel structures with high-speed serial interface SerDes. The Genetic Algorithm (GA) is optimized by adding a selection and substitution procedure. The optimized GA is applied to the common-source amplifier. The low-frequency gain, bandwidth, and slew rate target circuit optimization design is completed. Finally, the Clock and Data Recovery (CDR) circuit in SerDes is analyzed and designed. The CDR structure based on phase selector/phase interpolator type is used as the CDR circuit of the high-speed serial interface so that the final circuit function and performance meet the requirements. Through simulation experiments, it is found that the optimized GA can ensure that the evolved parameters allow the transistor to work in the saturation region to complete the circuit optimization design of the common-drain amplifier. After 250 generations of evolution, the maximum gain of 0.75 is roughly achieved at an input voltage of 1.2V and a MO transistor width of 20μm. The energy consumption per bit of data in the circuit based on the optimized GA is 16.8 pJ, 19.6% lower than the 20.1 pJ of the conventional circuit before optimization. The multi-objective circuit optimization design with a moderate gain is realized

本研究旨在解决以高速串行接口SerDes替换低效传统并行架构的复杂设计难题。通过新增选择与替换流程对遗传算法（Genetic Algorithm，GA）进行优化，并将优化后的GA应用于共源放大器（common-source amplifier），完成了面向低频增益、带宽及压摆率的目标电路优化设计。最后对SerDes中的时钟数据恢复（Clock and Data Recovery，CDR）电路开展分析与设计工作，采用基于相位选择器/相位插值器架构的CDR电路作为高速串行接口的CDR电路，使最终电路的功能与性能均满足设计要求。通过仿真实验发现，优化后的GA可确保演化得到的参数使晶体管工作于饱和区，进而完成共漏放大器（common-drain amplifier）的电路优化设计。在经过250代演化后，当输入电压为1.2V、MO晶体管宽度为20μm时，可实现约0.75的最大增益。基于优化后GA的电路，其单位数据比特能耗为16.8皮焦（pJ），较优化前传统电路的20.1皮焦降低了19.6%。最终实现了具备适中增益的多目标电路优化设计。