An Efficient Method for the Design of a Look-Up-Table (LUT) using Reversible Fault Tolerant Gates

This data presents the design of a reversible fault tolerant architecture for LUT (Look-Up-Table). A new 6×6 fault tolerant reversible gate is introduced for the design of an efficient LUT. The proposed design achieves the improvement in terms of number of gates, Quantum cost and unit delay compared to the best known existing approach. The proposed LUT can be used to implement any combinational Boolean function with minimum number of transistors which satisfies the fault tolerant property.