Optimization of Posit Multiplication Unit Based on Improved Wallace Tree

The Posit format, a novel floating-point representation, offers significant advantages over the IEEE 754 standard in terms of dynamic range and rounding error management. However, its hardware implementation, particularly the design of the mantissa multiplier, poses challenges. Therefore, this paper introduces an enhanced Wallace tree algorithm named 3L-Wallace tree, which reduces the number of stages in partial product summation, thereby decreasing both hardware resource consumption and overall latency. This improvement is achieved by adding specific counters, redesigning the layout of the partial product summation stage counters, and enhancing the adders used in the final summation stage. Furthermore, the paper implements the 3L-Wallace tree in the optimization of the Posit multiplication unit. Additionally, a modular design approach is introduced, dividing large bit-width multipliers into smaller, more manageable modules, thereby simplifying the design process and easing implementation difficulties. A dynamic selection algorithm is also designed, which dynamically selects multipliers of appropriate bit-width based on runtime mantissa width to avoid hardware resource waste. Experimental results show that the 3L-Wallace tree algorithm reduces hardware resource consumption by an average of 9.5%, power consumption by an average of 8.1%, and latency by an average of 10.4%, outperforming traditional methods, particularly in the implementation of large bit-width multipliers.