SCL + scr vse zivo.acq
收藏Figshare2020-01-08 更新2026-04-08 收录
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https://figshare.com/articles/SCL_scr_vse_zivo_acq/11551224/1
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资源简介：
The data are time series of EDA simulator output when connected to a DAQ system. The simulator's settings were tested when connected to a fixed resistor.
创建时间：
2020-01-08
