Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability [DATASET and Source Code]

Thanks for your interest in our work!

In order to facilitate your assessment and replication, we provides the dataset and source codes (verilog/python model/matlab) of our work (OIPUF) here. 

By the way, our latest work (SOI PUF and cSOI PUF) published in IEEE TIFS (2024) is based on OIPUF. 

If you have any questions, please feel free to contact with us: [e-mail] / [e-mail]

Full text about OIPUF can be downloaded from https://ieeexplore.ieee.org/document/10103139

Full text about SOI PUF and cSOI PUF can be downloaded from https://ieeexplore.ieee.org/document/10458688

Source code and FPGA project of SOI PUF and cSOI PUF can be download from https://github.com/yg99992/SOI_PUF. 

Matlab code

matlab/Generate_OI_block.mThis is a matlab manuscript used for generating the verilog code of random OI block.

matlab/OIPUF_64x4_placement.mThis is a matlab function used for generating XDC file for constraining the placement of (64,4)-OI block

matlab/OIPUF_64x8_placement.mThis is a matlab function used for generating XDC file for constraining the placement of (64,8)-OI block

matlab/OIPUF_placement_example.mAn example manuscript used for demonstrating the usage of OIPUF_64x4_placement.m and OIPUF_64x8_placement.m

Python code

python/puf_models.pyThe python models of XOR PUFs and OIPUFs, which can be used to generate CRPs.

for example:

from puf_models import oi_puf

# generate a (64,4)-OIPUF and further use the generated OIPUF to generate 1M CRPs
crps, puf_instance = oi_puf.gen_CRPs_PUF(64, 4, 1_000_000)  

python/attack_pypuf.pyA manuscript used to conduct to ANN attack on XOR PUF and OIPUF ('pypuf' package should be installed correctly).

Verilog code

verilog/OIPUF_64_4/All the verilog files of (64, 4)-OIPUF

verilog/OIPUF_64_8/All the verilog files of (64, 8)-OIPUF

CRP datasets extracted from FPGA

It consists of 13 CRP files (All the CRPs are extracted from FPGA):

FPGA_CRPs/FPGA3_CHAL_100M.csvThe 100 million 64-bit challenges

FPGA_CRPs/FPGA3_k4_PUF0.csvThe 100 million 1-bit responses extracted from (64,4)-OIPUF0

FPGA_CRPs/FPGA3_k4_PUF1.csvThe 100 million 1-bit responses extracted from (64,4)-OIPUF1

FPGA_CRPs/FPGA3_k4_PUF2.csvThe 100 million 1-bit responses extracted from (64,4)-OIPUF2

FPGA_CRPs/FPGA3_k4_PUF3.csvThe 100 million 1-bit responses extracted from (64,4)-OIPUF3

FPGA_CRPs/FPGA3_k4_PUF4.csvThe 100 million 1-bit responses extracted from (64,4)-OIPUF4

FPGA_CRPs/FPGA3_k4_PUF5.csvThe 100 million 1-bit responses extracted from (64,4)-OIPUF5

FPGA_CRPs/FPGA3_k8_PUF0.csvThe 100 million 1-bit responses extracted from (64,8)-OIPUF0

FPGA_CRPs/FPGA3_k8_PUF1.csvThe 100 million 1-bit responses extracted from (64,8)-OIPUF1

FPGA_CRPs/FPGA3_k8_PUF2.csvThe 100 million 1-bit responses extracted from (64,8)-OIPUF2

FPGA_CRPs/FPGA3_k8_PUF3.csvThe 100 million 1-bit responses extracted from (64,8)-OIPUF3

FPGA_CRPs/FPGA3_k8_PUF4.csvThe 100 million 1-bit responses extracted from (64,8)-OIPUF4

FPGA_CRPs/FPGA3_k8_PUF5.csvThe 100 million 1-bit responses extracted from (64,8)-OIPUF5