FOSID (FPGA On-chip Sensor IDentification): A dataset of signatures from the internal monitoring sensors of Xilinx Artix-7 chips (Basys-3 FPGA development boards) during the stimulation of their electronic activity with HW stimulus

The FOSID (FPGA On-chip Sensor IDentification) dataset comprises 88,000 raw sensor signatures collected from 22 Basys-3 FPGA development boards, each integrating a Xilinx Artix-7 chip. The data is structured in a five-dimensional tensor of shape (22, 5, 4, 200, 4000) per workload, where each dimension corresponds to: device_idx ∈ [0..21]: individual device identifier. zone_idx ∈ [0..4]: physical placement region of the hardware workload within the FPGA die. sensor_idx ∈ [0..3]: sensor type – TEMP, VCCAUX, VCCBRAM, and VCCINT. signature_idx ∈ [0..199]: index of each acquired signature per configuration. sample_idx ∈ [0..3999]: individual sample within a signature (sampled at ~120.2 kHz) Four different hardware workloads were implemented and used to stimulate the FPGA fabric during acquisition: AES, FFT, and two variants of matrix multipliers (UMM). Each implementation corresponds to a dedicated group in the HDF5 structure (i.e., AES_4K, FFT_4K, UMM_4K_ALLOC, UMM_4K_NOALLOC), and includes its own dataset with the same layout and metadata. Additionally, a one-dimensional dataset named device_uuids maps each device_idx to its unique 20-byte identifier, ensuring traceability of the samples. All sensor readings were stored as 32-bit floats, converted from ADC raw values (12-bit resolution) using the following calibration formulas (stored as attributes): Temperature: Celsius = ((ADC_code × 503.975) / 4096) – 273.15 Voltage: Voltage = (ADC_code / 4096) × 3 This dataset provides a comprehensive and high-resolution capture of internal sensor behavior across diverse conditions, including variations in workload, placement, and device-specific factors. Its volume and structure enable robust statistical analysis and machine learning-based fingerprinting.