CML DATA

In this paper, a lightweight optimization method for complex analog integrated circuits (ICs) is proposed based on convolution neural network (CNN)-multilayer perceptron (MLP) and particle swarm optimization (PSO) algorithm. According to the circuit structure and the proposed design specifications, the circuit is divided into several sub-module circuits. Then, the sub-module and overall dataset are constructed. CNN-IC models are trained to extract the ‘transistor-circuit module-integrate circuit’ features level by level of sub-module circuits, and the global MLP models are constructed based on the established CNN-IC models. Based on the lightweight models, the parameters of analog ICs are optimized by the constrained PSO algorithm. The verification has been conducted on Cadence software, and the circuit performance meets all design specifications. Compared with ANN-opt method, the dataset and simulation time can be decreased 91% and 95%, and the optimized power consumption can be decreased 17%. Meanwhile, compared with the RL algorithm, the optimization time can be decreased 89.6%, and the optimized power consumption can be decreased 29.5% under the same dataset. The results show that the proposed lightweight optimization method can greatly decrease the dataset and simulation time, and improve the optimization efficiency of analog ICs.本研究提出了一种基于卷积神经网络（CNN）-多层感知器（MLP）和粒子群优化（PSO）算法的轻量级优化方法，用于复杂模拟集成电路（IC）的设计。根据电路结构和所提出的设计规范，电路被划分为若干个子模块电路。随后，构建了子模块及整体数据集。通过训练CNN-IC模型，以逐级提取子模块电路中的‘晶体管-电路模块-集成电路’特征，并基于已建立的CNN-IC模型构建全局MLP模型。基于轻量级模型，利用约束PSO算法对模拟IC的参数进行优化。在Cadence软件上进行了验证，电路性能满足所有设计规范。与ANN优化方法相比，数据集和仿真时间可分别降低91%和95%，优化后的功耗降低17%。同时，与强化学习（RL）算法相比，在相同数据集下，优化时间可降低89.6%，优化后的功耗降低29.5%。结果表明，所提出的轻量级优化方法能显著降低数据集和仿真时间，并提高模拟IC的优化效率。

搜集汇总

背景与挑战

背景概述

CML DATA是一个用于模拟集成电路（IC）轻量级优化的数据集，发布于2024年。该数据集支持基于卷积神经网络（CNN）、多层感知器（MLP）和粒子群优化（PSO）算法的混合方法，旨在通过分层特征提取和模型构建，优化电路参数并显著减少数据集大小和模拟时间（例如，与现有方法相比可减少高达95%）。数据集包含子模块和整体数据，文件大小为390.04 KB，但访问需要IEEE DataPort订阅。