Performance improvement and power reduction techniques of on-chip networks

On-chip networks (a.k.a. networks on-chip or NoCs) have become the key communication media for modern many-core platforms. With tens to hundreds of cores integrated onto current and future many-core processors, a scalable NoC design with high performance and low power consumption is crucial for researchers to better utilize on-chip cores and achieve an efficient computing system. First and foremost, NoC performance improvement is of paramount importance. The performance of a NoC mainly refers to its average packet latency, which greatly influences the actual runtime of the attached many-core system. Therefore, on-chip packet latency is always among the most principal criteria of NoC designs. Another NoC design factor which is equally important, if not more, is the NoC power consumption. Recent studies as well as real-chip experiments show that NoC components can draw a substantial percentage of the overall chip power. Furthermore, this power consumption percentage of traditional on-chip networks increases with the growing core count and technology scaling. ❧ This research aims at providing performance improvement and power consumption reduction solutions for on-chip networks. First, several methods to reduce average on-chip packet latencies through application mapping are proposed, which intelligently assign running threads onto physical tiles to improve NoC performance, considering various scenarios and constraints of many-core platforms. Second, this research presents a novel NoC topology design methodology by selectively inserting express links onto mesh-based networks, aiming at minimizing on-chip latency for general-purpose many-core processors with no power overhead. These two topics focus on NoC performance improvement. Third, this research provides a proactive power gating method for on-chip routers. Specifically, a core state-aware power gating method for express link-based NoCs is first proposed, which utilizes the rich connectivity of express link-based networks as well as the knowledge of currently sleeping cores to selectively power gate routers, reducing NoC static power consumption with minimum latency overheads. Finally, a generic analysis of NoC proactive power gating is conducted for mesh-based NoCs, which identifies the trade-off between dynamic power consumption and static power consumption. Three efficient heuristic algorithms are then proposed for mesh-based NoC power gating, targeting the situations of minimum active routers, high-performance applications, and minimum overall power consumption, respectively.