A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS

This paper presents a reconfigurable 4.75-to-32 GBuad transmitter (TX) that operates up to 64Gb/s with fourlevel pulse-amplitude modulation (PAM-4) and at 32Gb/s with non-return-to-zero (NRZ) modulation scheme, designed in the 28-nm CMOS technology. The TX incorporates a quarter-rate architecture with a tap coefficient flexible feed-forward equalizer (FFE) up to 3 FFE taps. The TX employs a tailless CML driver with common-mode feedback (CMFB) for output swing control which provides 0.8 Vpp output swing, and a helical wiring T-coil for bandwidth expansion. The clock path of the TX includes the duty-cycle detection/correction (DCD/DCC) circuits with a resolution of sub-60fs and quadrature-error detection/correction (QED/QEC) circuits, and a LC phase locked loop (PLL) with a local injection-locked (IL) quadrature clock generation circuit. The TX operating at 64 Gb/s in PAM-4 modulation consumes 76.7 mW from 1-V supply with 0.8 Vpp, achieving an 1.2 pJ/b energy efficiency. The TX front end occupies an active area of 0.063 mm2.