Supplementary Dataset and Benchmark Logs: Energy-Efficient SIMD-Accelerated Expression Parsing

This repository contains the supplementary materials and experimental data supporting the research article: "Energy-Efficient SIMD-Accelerated Expression Parsing: A Cross-Architectural Microarchitectural Analysis in Managed Environments". The dataset is divided into three primary components: the raw microarchitectural hardware telemetry, the evaluated ablation methodologies, and a summary of the key empirical findings across modern AMD Zen 4 and Intel Tiger Lake platforms. 1. Experimental Benchmarks and Hardware Telemetry This section contains the comprehensive execution logs utilizing the BenchmarkDotNet framework on a .NET 10 managed runtime environment. File amd_zen4_performance_pass.md: Contains uncontaminated execution latency logs (Mean, Median, StdDev) for the AMD Ryzen 7 PRO 7840U during the pure "Performance and Power Pass". These base latency metrics (t) bypass profiler overhead and serve as the foundation for the Energy (E) and Energy-Delay Product (EDP) calculations, utilizing a continuous package power draw of ~17.85 W captured via AMD uProf. File intel_tigerlake_performance_pass.md: Contains the corresponding uncontaminated execution latency logs for the native 512-bit Intel Core i5-11400H platform during the pure performance evaluation. File amd_zen4_instrumentation_pass.md: Documents the deep diagnostic metrics extracted during the "Instrumentation Pass" on the AMD platform. It includes Performance Monitoring Unit (PMU) counters such as Total Cycles, Instruction Retired, Branch Mispredictions, Cache Misses, and Garbage Collection allocations (Gen0, Gen1, Allocated Bytes). File intel_tigerlake_instrumentation_pass.md: Contains the comparative execution latency and memory allocation diagnostics for the native 512-bit Intel Core i5-11400H platform. Files amd_zen4_performance_pass_timechart.csv and intel_tigerlake_performance_pass_timechart.csv: Provide the raw tabular time-series data and charting metrics associated with the performance execution across the evaluated pipelines, allowing for independent visualization and temporal analysis. File amd_zen4_complexity_multiplier.md: Contains the algorithmic scalability and memory diagnostic logs, evaluating pipeline performance and Garbage Collection pressure under increasing structural complexity multipliers (10x and 100x). 2. Evaluated Methodologies (Ablation Study) The benchmark data systematically isolates distinct parsing stages to test the following execution paths: ParseOnly: Contrasting traditional character-by-character scalar tokenization (ScalarParse) against a branchless AVX-2 accelerated classification method (SimdParse). ConvertOnly: Evaluating traditional stack-based operations (ShuntingYardConvert) versus flat-array prefix scanning (ScanBasedConvert) for algorithmic cache locality. EvalOnly: Comparing postfix numeric evaluation across Scalar, 256-bit (Vector256Eval), and 512-bit (Vector512Eval) SIMD execution lanes. FullPipeline: End-to-end combinatorial testing of the complete expression parsing pipelines (e.g., SimdTokenizerVector256Full) against the baseline .NET DataTable.Compute engine. 3. Key Findings Highlighted in the Data The AVX-512 Paradox & Energy Penalty: The empirical logs demonstrate that evaluating via 512-bit registers (Vector512Eval) on the AMD Zen 4 mobile architecture incurs a latency and CPU cycle penalty compared to 256-bit execution (Vector256Eval) due to microarchitectural double-pumping constraints. EDP Degradation: Given the measured static power envelope of ~17.85 W, this latency regression directly translates to a ~23.3% degradation in the Energy-Delay Product for the 512-bit vector path. Neutralizing Garbage Collection: The integration of zero-allocation SIMD data structures reduces end-to-end transient memory allocations from 13,368 Bytes down to 1,216 Bytes per operation. Race-to-Sleep: This severely curtails GC-induced active core wake-ups, minimizing dynamic power waste and preserving the processor's energy-efficient "race-to-sleep" states. Lexical Branch Predictability: Hardware counters reveal that replacing conditional scalar logic with SIMD bitmask extraction (TrailingZeroCount) in the tokenization stage reduces overall CPU cycles and branch mispredictions, further contributing to optimal energy efficiency.