Optimizing power delivery networks in VLSI platforms

Power delivery network (PDN) is an essential part of VLSI platform to deliver power to all devices in a platform from a power source. Because the PDN inevitably dissipates power that can result in a considerable amount of power loss in a platform, minimizing the power loss of the PDN has become an important issue in VLSI platform designs. This dissertation presents optimization methods to minimize the power loss of the PDN, and hence, improve the power efficiency of the PDN. Both circuit‐level and system‐level approaches are discussed along with the proposed methods that are verified at three specific VLSI platforms: smartphones, chip multi‐core processors (CMPs) and OLED display platforms.