Multi-Gate In-plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs Figure Data

Data used to produce figures 5-7 in the paper Multi-Gate In-plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs as well as tables 1 and 2. Figure 5 shows input and output data collected from a 3-input NAND gate comprised of a novel multi-gate (multi-input relay). Figures 6 and 7 present data from COMSOL simulations indended to outline a procedere for optimizing these relays and allow for scaling of the device parameters. Table 1 compares our designs with those of other works, in terms of number of relays and critical path. Table 2 compares the parameters of actual fabricated structures with those of the simulations.

本数据集包含用于生成论文《基于多门平面驱动纳米机电继电器的高效互补逻辑门设计》中图5-7及表格1和2的原始数据。图5展示了由一种新颖的多门（多输入继电器）构成的3输入与非门的输入与输出数据。图6和图7呈现了COMSOL仿真数据，旨在概述优化这些继电器的步骤并允许对设备参数进行缩放。表格1比较了我们的设计与其他作品的继电器数量和关键路径。表格2对比了实际制造结构的参数与仿真参数。